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Component Design Engineer


This is a Full-time position in Phoenix, AZ posted May 1, 2021.

**Job Description**About the team:The position offered is for a Design Automation Engineer in the Custom Layout Team of the Process Design Kit (PDK) group, within the Design Enablement (DE) organization.

Responsibilities are focused around development and support of PDK components relating to Custom Layout, primarily EDA technology files and parameterized cell development.

The team plans, executes, deploys, and supports these solutions in a timely manner.

Development and automated QA flows involve writing efficient code in scripting languages to automatically translate Intel process technology rules and requirements into vendor specific technology library file formats.About the role:We are looking for a highly motivated and responsible engineer to join our team to work on development of In die Variation probe cells (IDV), Electrostatic Discharge cells (ESD), Through Silicon Via cells (TSV) and boundary cells (HALO) designs.Responsibilities may include but not limited to:+ Developing APR test cases+ Running and debugging RV flows for ESD and TSV wrappers+ Working with layout designers+ Generating schematics+ Updating layout, and running LV flows**Qualifications**You must possess the below requirements to be initially considered for this position.

Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.Minimum requirements:Possess a bachelor’s with 1+ year industry experience or Master of Science degree in Electrical Engineering, Computer Science, or Computer Engineering.

Must have the required degree by May 2021.Experienced in the following areas:+ Backend designer with experience in RTL to GDS (Graphic Data Stream) flows using Synopsys ICC2.+ Reliability Verification (RV) flows using Apache Software (totem).+ Programming languages such as C++, Python, Ruby, or Tcl+ Experience in using the UNIX/Linux operating system+ Modeling layout design rule conceptsPreferred:+ Cadence-virtuoso+ Semiconductor devices physics+ Internal RV flow such as SAMS EM, RapidESD, VortexESD, Gradual aging, and Dynamic EOS_#designenablement_**Inside this Business Group**As the world’s largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art –
– from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.

Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth**Other Locations**US, California, Folsom;US, California, Santa Clara;US, Oregon, Hillsboro**Posting Statement**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.